Integrated Circuit. Transistor Transistor Logic (TTL). 4−Line−to−16−Line Decoder /Demultiplexer. 24−Lead DIP Type Package. Description: The NTE is a. 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test . datasheet, circuit, data sheet: NSC – 4-Line to Line for Electronic Components and Semiconductors, integrated circuits, diodes, triacs.
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Will someone please explain the purpose of inverting the outputs 0 through 15 as well as the use the NAND gates here? First, the inversion of the outputs simply means that the output is active low. That is, for an input ofthe 0 output is selected, and it is driven low. All the other ouputs stay high. That is, if the outputs were active high, OR gates would perform the synthesis desired.
Since the ouputs are active low, NAND gates do the job.
4 Line to 16 Line Demultiplexer / Decoder
The active-low enable datasheeet allow cascading of demultiplexers over many bits. If you wanted to generate a 1 of demultiplexer, you could use 16 s looking at the 4 least significant bits, while a single would look at the 4 most significant bits, with one ouput going to each of the other 16 s.
And why are there 2 of them, you ask? Rather than providing only a single enable, both pins are used. This allows more flexibility in iv logic functions available.
Dattasheet TTL parts and older memory chips have active low enable inputs, so the active low outputs of this part can be connected directly to those inputs. There are probably two enable inputs because otherwise there would be two unused pins on the 24 pin package I don’t recall seeing 22 pin DIP packages. The active-low output is just how the design for that specific decoder was carried out – there is also active-high varieties. As for the NAND gates, there is a function being implemented in which the gates are there to realize it.
4 to 16 decoder logic diagram – Electrical Engineering Stack Exchange
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I am a new user so I didn’t know I had that power. So is it possible that both enables are hooked to a 2-input OR gate; this is just making use of the extra pins to make 24?
According to the internal logic diagram on the datasheet, the G inputs are connected to a two-input AND gate with inverting inputs, whose output feeds one input of all the NAND gates that produce the outputs.