Integrated Circuit. Transistor Transistor Logic (TTL). 4−Line−to−16−Line Decoder /Demultiplexer. 24−Lead DIP Type Package. Description: The NTE is a. 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test . datasheet, circuit, data sheet: NSC – 4-Line to Line for Electronic Components and Semiconductors, integrated circuits, diodes, triacs.

Author: Kesar Disar
Country: Gabon
Language: English (Spanish)
Genre: Photos
Published (Last): 27 December 2017
Pages: 338
PDF File Size: 8.16 Mb
ePub File Size: 12.25 Mb
ISBN: 365-9-19813-837-9
Downloads: 17350
Price: Free* [*Free Regsitration Required]
Uploader: Zulkis

By using our site, you acknowledge that you have read and understand our Cookie PolicyPrivacy Policyand our Terms of Service.

Will someone please explain the purpose of inverting the outputs 0 through 15 as well as the use the NAND gates here? First, the inversion of the outputs simply means that the output is active low. That is, for an input ofthe 0 output is selected, and it is driven low. All the other ouputs stay high. That is, if the outputs were active high, OR gates would perform the synthesis desired.

Since the ouputs are active low, NAND gates do the job.

4 Line to 16 Line Demultiplexer / Decoder

The active-low enable datasheeet allow cascading of demultiplexers over many bits. If you wanted to generate a 1 of demultiplexer, you could use 16 s looking at the 4 least significant bits, while a single would look at the 4 most significant bits, with one ouput going to each of the other 16 s.


And why are there 2 of them, you ask? Rather than providing only a single enable, both pins are used. This allows more flexibility in iv logic functions available.

National Semiconductor

Dattasheet TTL parts and older memory chips have active low enable inputs, so the active low outputs of this part can be connected directly to those inputs. There are probably two enable inputs because otherwise there would be two unused pins on the 24 pin package I don’t recall seeing 22 pin DIP packages. The active-low output is just how the design for that specific decoder was carried out – there is also active-high varieties. As for the NAND gates, there is a function being implemented in which the gates are there to realize it.

If you want to know exactly what is going on then draw out the truth table, but it is unlikely their function will make much sense to you. By clicking “Post Your Answer”, you acknowledge that you have read our updated terms of serviceprivacy policy and cookie policyand that your continued use of the website datawheet subject to these policies.

4 to 16 decoder logic diagram – Electrical Engineering Stack Exchange

Home Questions Tags Users Unanswered. My first question is more important WhatRoughBeast 49k 2 28 Please consider upvoting those questions you found useful like this one by clicking the arrow pointing up near the answer vote count which is in turn above the checkbox you clicked to accept this question.


The person who took time to answer the question will appreciate that. You can upvote more than one answer.

I am a new user so I didn’t know I had that power. So is it possible that both enables are hooked to a 2-input OR gate; this is just making use of the extra pins to make 24?

According to the internal logic diagram on the datasheet, the G inputs are connected to a two-input AND gate with inverting inputs, whose output feeds one input of all the NAND gates that produce the outputs.

Sign up or log in Sign up using Google. Sign up using Facebook. Sign up using Email and Password. Post as a guest Name. Email Required, but never shown. Post Your Answer Discard By clicking “Post Your Answer”, you acknowledge that you have read our updated terms of serviceprivacy policy and cookie policyand that your continued use of the website is subject to these policies.