74HC Datasheet, 74HC stage Binary Counter Datasheet, buy 74HC, 74HC pdf, ic 74HC description/ordering information. The ‘HC devices are stage asynchronous binary counters, with the outputs of all stages available externally. A high. Data sheet acquired from Harris Semiconductor. SCHSD. Features. • Fully Static Operation. • Buffered Inputs. • Common Reset. • Negative.
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So, what the heck, I’ll look at timing before slapping something together. Here’s a simplified schematic of the guts of the VGA framebuffer it ignores the reset and connections between the two ”s required to generate 19 bits of address.
The dot clock is In the schematic above, the ‘ counters increment the address on the rising edge of the daatasheet, while the ‘ d-flop captures the data from the last address before it changes. I’m going to ignore those timing calculations for the moment next log because there’s an even bigger problem here – it takes too long for the address to settle.
I’m using typical values for the moment; if it doesn’t work there, it’s not going to work worst-case, either.
I Hate Ripple Counters | Details |
Since it’s a ripple counter, Q0 flips, then Q1, then Q2, etc, so we have to add all the delays so see how long it takes for the datashee to settle to the next value. This also ignores the fact that two 74HCs need to be chained to generate the bit address: I haven’t used VHC logic before, but keep seeing it around.
Surely the 74VHCwith its Mhz typical max clock frequency datashset do the job!
Let’s run the numbers, using a 15pF load: So, with two of them connected to generate 19 bits of address, the tpd from datssheet clock edge to the MSB settling is: Add in the 12 ns access time of the SRAM, and we’re definitely over budget. It’s a shame, because the ‘ packs bits into a single package.
74HC data sheet datasheet & applicatoin notes – Datasheet Archive
I have to go take them out of my shopping cart now: The 74VHC is another candidate – it has twin 4-bit counters in a package, so three ICs would be necessary. I started with the VHC part this time: For Qd the fourth bitthe typical tpd is given as 8. Synchronous counters use extra logic to form the next state from the previous one directly, without waiting for clocks to ripple through, so the outputs settle faster.
Now, I need 5 ICs to make the counter – if it’s even fast enough. Interestingly, it also has a synchronous clear, and connections for synchronous expansion between counters with lookahead carry outputs. If I’m reading the datasheet correctly, the maximum delay from clock edge to valid outputs is This would work – with the 12ns SRAM access time, still way under the 40ns cycle time. How about the 74HC? Doesn’t look promising – although the typical 21ns 6V or 25ns 4.
If I were going to build a bunch of these, I’d try harder to get the 74HC to work.
I need 5 of them, which sucks. The clock input on the ‘ works on the positive edge, so the schematic above changes a bit, but at least the addresses seem OK.
Next step – the rest of the logic and timing calculations. What about using the 74ch4040 PIC available and bitbanging the address lines?
Even if you could output a new address every cycle, that’s still only about half of the Maybe a fast external counter for the lowest 4 or 8 bits, and the PIC generates the upper ones? Synchronization is an issue, but it’s worth thinking about – maybe if the PIC runs from the external This could be interesting. All these numbers involving multiples of propagation-delays are making me question even further how I got the ol’ LCD controller dwtasheet. Musta been a bunch of pixie-dust in there, or a poor memory of 18 years ago.
Interesting discovery upon looking back I can hook one to the four-channel scope and have a look at the delays between the LSB and successive bits. I spent the afternoon re-working my ugly SOIC adapter board designs to reduce the ground-connection impedance and add on-board bypass caps. They’re not completely general anymore, since now they assume standard corner pin supply connections, but they should be better for signal integrity.
Monitors can handle some clock frequency variations. The row address can be updated adtasheet the horizontal sync. That should relax some timing as your MSB are no longer rely on the propagation from the lower bits. I saw the 25 MHz trick in your terminal project – good to know. I have a tube of 50 MHz cans around here that I could divide down, but since I have to order parts for this thing anyway, I might as well pick up the exact frequency for a few bucks.
If I were making more than a one-off project, I think the 25 MHz idea might be the way to go. Cycling back the hsync for a second counter is interesting. I’ll have to give that one some thought. Yeah, I had read about keeping video blanked outside of the active area. In the store-each-dot-period-as-a-byte plan, this is trivial – I have full and easy control of all the singals on on a per-dot basis.
In this case, it’s not memory but registers. I think either one would definitely work, and it would make an interesting project, but I’ve somehow got it into my head that I 74hf4040 actual x Yes, delete it Cancel. About Us Contact Hackaday.
I Hate Ripple Counters
VHC to the rescue? Synchronous Counters Synchronous counters use extra logic to form the next state from the previous one directly, without waiting for clocks to ripple through, so the outputs settle faster.
Did I miss something on the ripple counters? Maybe I’m doing this wrong? Sign up Already a member? Don’t forget that ground-bounce!
Those bounces won’t kill this project. I’m already bummed about the color thing